System design caching
Cache aside, stampede, TTL
Stampede, dogpile, jittered TTL, singleflight. Sketch the miss path.
Stampede, dogpile, jittered TTL, singleflight. Sketch the miss path.
What lives at the edge. Invalidation. Stale-while-revalidate.
LC 146. Hash map + DLL. Get and put both O(1). Then add thread-safety notes.
Origin p99 80ms, cache 2ms. What hit rate keeps blended p99 under 20ms?